Question:
What is "cas latency", and is it better to have it high or low?
AK
2009-05-29 10:18:13 UTC
I'm building a computer, and every time I look RAM, I see "cas latency" under specifications.

What is "cas latency", and is the RAM better/faster if it has a higher cas latency, or is it better to have lower cas latency?
Three answers:
vic5014
2009-05-29 11:24:11 UTC
to expand on the previous answer, cas latency is often referred to as memory timings on computer enthuasist websites. lower latency is always better and ddr3 has higher latency than ddr2. ddr2 has higher latency than ddr1, but ddr1 isn't used much anymore. ddr2 latencies are usually 4 or 5. ddr3 latencies are around 7-9. faster (higher clocked) ram usually has higher latency ratings and higher latency partially offsets the benefits of higher clock speed. ddr2 latency was pretty high when in first came out a few years ago, which is why is wasn't widely adopted then. it didn't really become mainstream until amd shifted to using it (intel was an early adopter), but its pretty mature now and the latency has come down a lot over time. the same will happen with ddr3.

finally, laptop ram usually has higher latency at the same speed. it also tends to be slower. for example the fastest laptop memory available on newegg is cas 9 ddr3 1333. by comparison, good desktop ddr3 1333 tends to have a latency of 7 and desktop ddr3 goes all the way up to ddr 3 2000 with cas latencies as low as 7. this is because lower-latency or higher-clocked ram often requires more voltage and laptops are very restricted in their ability to handle the extra heat this produces.
?
2016-10-06 12:31:17 UTC
Cas Latency
David B
2009-05-29 10:21:29 UTC
CAS (Column Address Strobe) latency (CL) is the delay time which elapses between the moment a memory controller tells the memory module to access a particular column in a selected row, and the moment the data from the given array location is available on the module's output pins.



In asynchronous DRAM, the interval is specified in nanoseconds. In synchronous DRAM, the interval is specified in clock cycles, and must be multiplied by the cycle time (i.e. divided by the clock frequency) to convert to nanoseconds.


This content was originally posted on Y! Answers, a Q&A website that shut down in 2021.
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